1. Field of the Invention
The present invention relates to a timer apparatus for a microcomputer, more specifically, it relates to a timer apparatus composed of a timer and its accompanying circuits, which are built, in a single-chip microcomputer and can be employed for controlling time events thereof.
2. Description of the Related Art
Referring to a block diagram of FIG. 1, an outlining explanation will be made concerning the conventional fundamental configuration of an individual timer built in a single-chip microcomputer.
In FIG. 1, reference symbol 1 indicates a timer. This timer 1 is built in a single-chip microcomputer, and as one of its peripheral circuits, it is used for controlling time events of the single-chip microcomputer.
The timer 1 is mainly composed of a counter 2 and a register 3.
The counter 2 executes a counting operation, with a clock signal CLK as a count source generated in the single-chip microcomputer in which the timer 1 is built in.
Data DATA (refer to FIG. 3) is supplied to the register 3 via a bus from a CPU of the single-chip microcomputer in which the timer 1 is built in. Then, at the time point when a register write signal W is supplied from the CPU, the register 3 takes in and holds the data DATA outputted from the CPU to the bus.
According to the data held in the register 3 as mentioned above, the timer 1 consequently causes the counter 2 to perform counting operation of the clock CLK, and accordingly carries out various counting operations. For example, when a load signal LOAD is supplied from the CPU to the counter 2, data held in the register 3 is set as the initial value in the counter 2. From the initial value thus set, with the clock signal CLK as a count source, the counter 2 starts a counting down from that time point onward, and when the count value becomes "0," an underflow signal UF is outputted. Then, through the output of this underflow signal UF from the counter 2, the CPU executes, for example, a predetermined interrupt processing, or peripheral circuits not illustrated are made to carry out various processings.
An external input signal indicated by the reference symbol EXIN is likewise supplied to the timer 1. Operations of the timer 1 are controlled, also by the external input signal EXIN supplied from the outside of the single-chip microcomputer in which the timer 1 is built in. By changing over the count source of the counter 2 to the external input signal EXIN which is a clock, replacing the ordinary single-chip microcomputer internal clock signal CLK, for example, it becomes possible for the single-chip microcomputer to perform non-routine operations.
Next, referring to the circuit diagram of FIG. 2, explanation will be made on a conventional circuit configuration for accessing the register 3 of the timer 1 so as to write data.
There are two kinds of access to the register 3, data write access for writing and holding data in the register 3, and data read access for reading out data held in the register 3, and since data write access is the object of the present invention, data read access will be omitted.
In FIG. 2, reference symbol 8 indicates a dual-input AND gate. To one of its input terminals a write signal 5, and to the other input terminal an "i"th-timer register address decoding signal 7, are inputted respectively. Consequently, when both input signals 5 and 7 are "1" in common, the AND gate 8 outputs a signal "1". The output signal of the AND gate 8 is supplied as an "i"th timer register write signal 9 to the register 3 of the timer 1. This "i"th timer register write signal 9 is the aforementioned register write signal W indicated in FIG. 1.
Suppose that within an ordinary single-chip microcomputer, a plurality of equivalents to the aforementioned timer 1 are provided. Now, for example, i (i=1, 2 . . . n) is assumed to be a number which specifies n number of individual timers 1 respectively, then the "i"th timer register address decoding signal 7 is assumed to be a signal which specifies the respective timers 1 ("i"th timer 1-i), and the write signal 5 is a signal for writing data into any of the registers 3 of the timers 1.
Consequently, in the case where the write signal 5 is active ("1"), since only from the AND gate 8 in which the "i"th timer register address decoding signal 7 has become active ("1"), the "i"th register write signal 9 is outputted, data is written into the register 3 only of the "i"th timer 1-i.
As mentioned above, an individual timer apparatus is composed of the circuit shown in FIG. 2 and the timer 1 shown in FIG. 1, and usually a plurality of such timer apparatus are built in the general single-chip microcomputer.
A block diagram of FIG. 3 shows an example of configuration of a case in which a plurality, for example, three first through third timers 1-1, 1-2 and 1-3 are built in such a conventional single-chip microcomputer.
In FIG. 3, reference symbols 50, 51 and 52 indicate, respectively, a CPU of the single-chip microcomputer, an address decoder, and an address bus which interconnects them, for sending an address signal ADD from the CPU 50 to the address decoder 51.
AND gates 8-1, 8-2 and 8-3, corresponding to reference symbol 8 of FIG. 2, have outputs respectively connected to each timer 1-1, 1-2 and 1-3.
Timer register address decoding signals 7-1, 7-2 and 7-3 from the address decoder 51 are respectively connected to one of the inputs of the respective AND gates 8-1, 8-2 and 8-3, and to the other, write signal 5 from the CPU 50 is connected in common.
Moreover, the respective registers 3 of the timers 1-1, 1-2 and 1-3 are connected with the CPU 50 through a data bus 53.
In such a configuration, an operation for specifying one among timers 1-1, 1-2 and 1-3 and writing data into its register 3 will be as follows.
The address signal ADD which specifies any of the timers 1-1, 1-2 and 1-3 is outputted from the CPU 50 to the address bus 52. For instance, in the present example shown in FIG. 3, the 2-bit address signal ADD is outputted from the CPU 50 to the address bus 52 and is inputted into the address decoder 51. Address decoder 51 decodes the address signal ADD supplied from the CPU 50 and converts to "1" only one among "i"th timer register address decoding signal 7-1, 7-2 and 7-3.
Furthermore, the CPU 50 changes the write signal 5 to "1", and simultaneously outputs to the data bus 53 data DATA to be written into the register 3.
Accordingly, only the "i"th timer register write signal 9-1 (or 9-2, or 9-3) becomes "1", which is the output from the AND gate 8-1 (or 8-2, or 8-3) to whose one input of the "i"th timer register address decoding signal 7-1 (or 7-2, 7-3) of "1" has been supplied. Consequently, data DATA from the data bus 53 is inputted and written into the register 3 of the first timer 1-1 (or second timer 1-2, or third timer 1-3), into which the "i"th timer register write signal 9-1 (or 9-2, or 9-3) of "1" is inputted.
In a conventional single-chip microcomputer which built in such timers, when the CPU writes data into the respective registers of a plurality of the built-in timers, the individual timers into which data must be written are specified one by one according to the address decoding signal, and writes the data only into the specified timer register. Consequently, when it is necessary to write identical data into the plurality of timer registers, it is necessary for the CPU to reiterate a process which writes identical data into the respective registers while successively specifying each timer. When there is no time margin in the program which is executed by the microcomputer, however, a situation arises in which the process of writing data into the timer does not catch up with the program execution speed.
The interrupt processing which is carried out at the time of a generation of an interrupt in the single-chip microcomputer, for instance, can be given as a concrete example of a situation as aforementioned. The process, which entails a generation of the interrupt and writing of data into the plurality of timer registers, is executed according to an interrupt operation which is separate from the main routine process of the single-chip microcomputer, but there is concern that the successive writing of data into the plurality of timer registers might become impossible due to the time aspect, since lack of a time margin in the main routine would cause a time control restriction to be imposed on the interrupt process.
For example, with the aforementioned configuration shown in FIG. 3, even when a time margin exists for the CPU to write data either into the individual timer registers, or into two timer registers among the three timers, there is a possibility that there is not sufficient time for the CPU to write data into every one of the registers of the three timers.
Moreover, when it is necessary to control the plurality of timers likewise with the external input signal, it becomes necessary to input the external input signal to the plurality of timers in the same manner, but herein, also owing to the time aspect, there is the concern that control would prove difficult.